Semiconductor Engineering

Best Practices For Power-Aware Verification: Because Designing For Low Power Is Only Half ...

As modern chips push the limits of power efficiency, power management has become a top priority. With today’s increasingly complex devices, verifying power intent isn’t just a technical requirement.
Semiconductor Engineering

Power Management And Integration Of IPs In SoCs: Part 1

IPs – whether in the form of soft or hard macros – are the epicenter of today’s SoC designs. Integration of IP with low power designs and conducting power aware (PA) verification are always complex ...
EDN

Verdi power-aware debug module enables visualization of power intent

PARIS — SpringSoft introduced a new power-aware debug module for its Verdi automated debug system, accelerating the comprehension of power intent and automating the process of visualizing, tracing and ...
EDN

Capturing and communicating power-efficient design knowledge

In recent years, power consumption has moved to the forefront of ASIC and system-on-chip (SoC) development concerns. The combination of higher clock speeds, greater functional integration, and smaller ...