Seeking an internship position during the summer of 2011 in the area of Digital ASIC Design with focus on Front-end design, Verification or Layout. Obtained Bachelor’s degree in Electronics ...

In this paper an optimized power gating design on a 55-nm Static Random Access Memory (SRAM) compiler is presented. Two low leakage modes: retention and sleep mode are discussed. The arrangement of ...

SAN MATEO, Calif. — With the rollout of its Star Memory System, an on-chip test and repair mechanism for embedded SRAM, memory compiler specialist Virage Logic Corp. is making good on its promise to ...