EDN

SystemVerilog assertions unify design and verification

The SystemVerilog standard is the result of an industry-wide effort to extend the Verilog language in a consistent way to include enhanced modeling and verification features. By adding verification ...
Design-Reuse

SystemVerilog 3.1 adds assertions and testbench automation

The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. It eliminates many of Verilog's past limitations, ...
EDN

Panelists: Verilog should selectively include assertions

SAN JOSE, Calif. — Simple assertions should be part of future Verilog IEEE standards, according to panelists at the DVCon Design and Verification Conference here Monday (Feb. 24). But several said ...
Design-Reuse

Synopsys Donates Library of Advanced SystemVerilog Assertion Checkers to Accellera ...

MOUNTAIN VIEW, Calif., July 26, 2006--Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, today announced that it has donated a library of advanced SystemVerilog assertion ...
Electronic Design

Functional Verification Tool Gains Link To SystemVerilog Assertions

With the addition of a standard assertion-language link, the 360 Module Verifier (360 MV), a functional verification environment, is equipped to fully leverage both SystemVerilog assertions and Open ...
Semiconductor Engineering

Working With Custom Checkers In Dynamic Simulation Of Low Power Designs

Power-aware simulators can provide a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA ...
Electronic Design

SystemVerilog: The Complete Solution

The electronics industry is constantly challenged by the ever-growing design and verification requirements for complex chips. With the IEEE-Std 1800-2005 System-Verilog standard, the industry has a ...