EDN

Memory fault models and testing

A different set of fault models and testing techniques is required for memory blocks vs. logic. MBIST algorithms that are used to detect faults inside memory are based upon these fault models. This ...
Semiconductor Engineering

Automation And Fault Simulation Of Safety-Critical FPGA Designs

Functional safety is a major challenge for field programmable gate arrays (FPGAs) and other semiconductor designs. Safety requirements go beyond traditional verification, which focuses on design bugs.
T&D

On-line Fault Detection to Prevent Network Failure

Schematic view of a typical Smart Cable Guard setup with a monitored cable section spanning multiple RMUs installed in medium-voltage/low-voltage substations. Medium ...