Design-Reuse

A custom RISC-V vector instruction to accelerate structured-sparse matrix multiplications

A novel AI-acceleration paper presents a method to optimize sparse matrix multiplication for machine learning models, particularly focusing on structured sparsity. Structured sparsity involves a ...
Electronics Weekly

riscvOVPsim gets Risc-V vector instructions

Imperas has extended its Risc-V reference model and simulator to cover forthcoming vector instructions and to support coverage-driven verification analysis. Called riscvOVPsim, the enhanced version ...
Forbes

SiFive Is Leading The Way For Innovation On RISC-V

The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...
Design-Reuse

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance ...

The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized ...
Electronics Weekly

riscvOVPsim gets Risc-V vector instructions

Imperas has extended its Risc-V reference model and simulator to cover forthcoming vector instructions and to support coverage-driven verification analysis. Called riscvOVPsim, the enhanced version ...
Liliputing

SiFive launches P470 and P670 RISC-V processors with vector instruction support

RISC-V chip designer SiFive is introducing two new processors that the company says are designed for high-performance, energy-efficient applications such as wearables, smart home devices, virtual ...
ExtremeTech

ARM guns for high-performance computing with its new vector instruction set

ARM has unveiled a new, highly flexible type of vector processing instruction that it plans to debut in HPC markets and businesses. Share on Facebook (opens in a new window) Share on X (opens in a new ...