NAPA, Calif. — Implementation of the new Verilog-2001 hardware description language became practical with the IEEE's release Wednesday (Oct. 17) of documentation that describes the standard, ...

San Jose, CA – February 20, 2001 – C Level Design, Inc. today announced a fully automated Verilog Programming Language Interface (PLI) and VHDL Foreign Language Interface (FLI) code generators to ...

Verilog was proprietary, while VHDL was open source, and competitors began pushing VHDL for IEEE standardization to break Cadence's stranglehold on logic simulation. The company responded by founding ...

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all promised by version 5.0 of the VERA ...