Today, functional verification consumes most of the time in the design of layered protocols like OSI Model, PCI Express, etc. As we think of reuse of design components, the reuse of verification ...

The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or ...

SAN FRANCISCO — The SystemVerilog Verification Methodology Manual (VMM), a book authored by verification experts from Synopsys Inc. and ARM Ltd. describing the use of SystemVerilog for verification, ...

This course covers the systematic design of real-time digital systems and verification techniques using field-programmable gate arrays (FPGAs). The course presents a top-down design methodology, where ...

I2C Verification IP provides an smart way to verify the I2C bi-directional two-wire bus. The SmartDV s I2C Verification IP is fully compliant with version 2.1, 3.0 and 6.0 of the Philip s I2C-Bus ...

There’s an old saying about simulation: “It’s all about the need for speed.” Simulation is the core technology for functional verification of semiconductors, and the demand for higher runtime ...

Standard cell libraries have been a mainstay of chip design for many decades since the inception of logic synthesis and composition methodologies. Cell library IP typically contains Verilog models ...

Sun's engineers modeled a complex cache-coherence protocol, with parallelism and multi-threading, for a high-performance processor. They also used a commercial formal property-checking tool from ...